Semiconductor Firm: A $50M Design Oversight
The Ten-Million-Dollar Mistake
In the spring of 2022, a design team at a major semiconductor firm discovered a timing error in a 5-nanometer chip three weeks before tape-out. The error was subtle, a misplaced via in a standard cell, but the cost of correction was not. New photomasks had to be ordered, at roughly ten million dollars per set. The delay pushed the product launch by a quarter, costing an estimated forty million in lost revenue. The team had considered switching electronic design automation (EDA) vendors the previous year, tempted by a competitor’s pricing, but had stayed with Cadence Design Systems. When the error was traced to a human mistake rather than a tool failure, the director of engineering noted, without irony, that the ten million dollars was a bargain compared to the risk of migrating design environments mid-project.
This is the economic terrain that Cadence occupies: a narrow but non-negotiable checkpoint in a supply chain where the cost of failure is measured in eight figures and the cost of software is rounding error. Cadence captures approximately 2.25 percent of the semiconductor industry’s revenue, a small tax on a $550 billion global market, by selling the software necessary to design advanced chips. Its business model rests on a simple mechanical truth: every two years, Taiwan Semiconductor Manufacturing Company (TSMC) introduces a new process node, and every company that wishes to remain competitive must redesign its silicon from scratch to exploit the new physics. Each redesign requires new licenses for Cadence’s tools. The result is a $3 billion revenue stream that behaves like a subscription to Moore’s Law itself, paid for by Apple, NVIDIA, Google, Amazon, Samsung, and an expanding cohort of non-traditional chip designers who have concluded that semiconductor differentiation is now a prerequisite for platform survival.
The Tax on Shrinking
The economics of EDA are best understood as a royalty on transistor density. For decades, semiconductor advancement has followed a predictable rhythm: smaller transistors, lower power, higher performance, delivered on a roughly twenty-four-month cadence. This cycle creates a forced march for design teams. A chip designed for TSMC’s 5-nanometer node cannot simply be shrunk to 3 nanometers; the physical rules change, lectromigration effects worsen, power delivery networks require complete re-architecture, and timing closure becomes a fundamentally different mathematical problem. Consequently, each node transition demands a full redesign, which in turn requires new versions of the software used to simulate, verify, and lay out the circuitry.
Cadence has positioned itself as the indispensable intermediary in this process. The company does not sell its tools as perpetual licenses; instead, it operates on a subscription model that aligns with these redesign cycles. Customers pay annual fees that grant access to continuous updates, ensuring that when TSMC releases a new process design kit (PDK), the software is already capable of handling the new constraints. This creates a revenue stream that is remarkably insensitive to the semiconductor industry’s notorious cyclicality. Even during downturns, design teams cannot skip node transitions without surrendering competitive position to rivals who do migrate. The result is a financial structure that resembles a utility more than a software company: recurring, predictable, and deeply embedded in the operational infrastructure of the customer.
Yet this stability masks a profound vulnerability. Cadence’s entire valuation assumes that Moore’s Law will continue its cadence indefinitely, or at least for the foreseeable future. If TSMC were to announce that the transition from 3 nanometers to 2 nanometers would take four years rather than two, whether due to physical limits, cost constraints, or a shift toward chiplet-based architectures that reduce the need for monolithic redesigns, the implications would be immediate. The company’s growth is not driven by increasing market share against its primary rival, Synopsys, but by the expanding surface area of semiconductor design itself. When the treadmill slows, the tax base erodes.
The Software Is the Factory
To understand why Cadence occupies this position, one must return to 1989, when the company was formed from the merger of two startups, EDA and SDA. The timing was not coincidental. The semiconductor industry was undergoing a structural disaggregation: the old model of vertical integration, where companies like Intel designed, manufactured, and packaged their own chips, was giving way to a fabless ecosystem. Companies wanted to design chips without building fabrication plants, but they needed software to simulate the manufacturing process before committing to silicon. Cadence provided the virtual factory.
This historical position created a moat that has proven impossible to cross. Building competitive EDA software requires three things that cannot be purchased or accelerated: decades of accumulated intellectual property describing the behavior of silicon at the atomic level; deep, trust-based relationships with foundries like TSMC, Samsung, and Intel that grant early access to process node specifications; and thousands of engineers who possess the rare intersection of software expertise and semiconductor physics. No startup has successfully challenged the Cadence-Synopsys duopoly in three decades. The barriers are not merely financial; they are temporal. One cannot code around twenty years of incremental refinement in parasitic extraction algorithms or placement optimization heuristics.
The duopoly structure defines every strategic decision Cadence makes. There is no viable third alternative for leading-edge design, which means that Cadence and Synopsys engage in a peculiar form of competition. They cannot compete on price, owering fees would simply trigger a race to the bottom that would destroy margins for both parties without expanding the market. Instead, they compete on capability coverage. A customer designing a complex system-on-chip (SoC) requires a complete toolchain: logic synthesis, physical design, signoff verification, emulation, and analog/mixed-signal design. If Synopsys offers a superior solution in one domain, say, AI-optimized digital place-and-route, customers will dual-source or switch, even if they prefer Cadence’s analog tools. Consequently, Cadence must maintain functional parity across every domain, which necessitates massive, continuous R&D expenditure. The two companies spend themselves into exhaustion to maintain a stalemate, and the industry pays for both.
The Subscription Trap
In 2008, this economic engine nearly seized. The financial crisis hit semiconductor R&D budgets just as Cadence was struggling with a product transition. Revenue collapsed, the stock fell below three dollars, and the entire management team resigned. The board installed Lip-Bu Tan as interim CEO, a move that would prove to be the most consequential economic intervention in the company’s history, not because of charisma or vision, but because of a mechanical change to the revenue model.
Prior to Tan’s arrival, Cadence sold perpetual licenses. Customers paid large upfront sums for software they could use indefinitely, then purchased maintenance contracts for updates. This created a destructive dynamic at the end of each fiscal quarter. Large customers like Intel and Texas Instruments knew that Cadence needed to book revenue to hit targets. They would withhold purchase orders until the final days of the quarter, extracting discounts of thirty percent or more. Revenue was lumpy, unpredictable, and increasingly unprofitable.
Tan’s team transitioned the company to a pure subscription model. Customers would pay annual fees, locked in for three-year terms, with no option to negotiate end-of-quarter discounts because there were no large perpetual license fees to discount. The transformation was painful, revenue initially appeared to decline as large upfront payments were replaced by smaller annual streams, but it fundamentally altered the company’s economic DNA. Cadence became a compounding annuity business rather than a transactional software vendor.
Yet this model contains its own constraint. By locking customers into multi-year subscriptions, Cadence eliminates its ability to capture windfall pricing during semiconductor booms. During the 2021–2022 chip shortage, demand for EDA tools was desperate. Companies were racing to tape out designs to capture supply-constrained market share. A vendor with perpetual licenses could have raised prices precipitously. Cadence, bound by subscription contracts, watched the frenzy from the sidelines, collecting its predictable 2.25 percent while the value of its product temporarily spiked far higher. The subscription model trades volatility for predictability, but it also caps the upside during the very moments when the software proves most indispensable.
The New Verticals
While the revenue model stabilized, the customer base was undergoing a structural transformation that few anticipated. Fifteen years ago, the semiconductor industry had a clear hierarchy: Intel, Qualcomm, and a handful of communication chip vendors designed the complex silicon; everyone else bought off-the-shelf components. Today, eight of the ten most valuable companies in the world design their own semiconductors. Apple builds the A-series and M-series chips that differentiate its devices. Google develops Tensor and TPU chips for AI inference. Amazon has Graviton and Trainium. Tesla designs its own Full Self-Driving chips. Even Ford has announced silicon design initiatives for its electric vehicles.
This represents a fundamental expansion of Cadence’s addressable market, but not in the traditional sense of market share gain. Cadence is not taking customers from Synopsys; rather, the pool of customers who must pay the EDA tax has grown. Each new entrant, whether a hyperscaler or an automotive OEM, adds a new R&D budget that must be spent on design tools. This is not a cyclical trend but a structural shift in competitive strategy. Platform companies have recognized that chip-level differentiation is now a core advantage, and they are bringing design in-house, creating a new tier of mega-customers with deep pockets and long-term horizons.
However, this democratization introduces friction. Traditional semiconductor companies employ armies of EDA experts who require minimal hand-holding. A company like Ford, entering chip design for the first time, lacks internal expertise in tool flows and methodology. They demand extensive support, training, and integration services. The revenue from these new customers comes with higher servicing costs and lower initial contract values, as they start with smaller design teams and simpler chips. Cadence faces a tension between volume growth and margin compression: the new verticals expand the top line but may not translate proportionally to profit if onboarding costs scale linearly with customer count.
The Price of Parity
The most acute tension in Cadence’s current strategy lies in the battle for digital supremacy. Historically, Cadence dominated analog and mixed-signal design: he tools used to craft radio frequency circuits, power management, and sensor interfaces. Synopsys owned the digital realm: logic synthesis and physical design for the massive digital SoCs that power smartphones and data centers. As artificial intelligence workloads have driven demand for massive digital chips, GPUs and AI accelerators, the center of gravity in EDA has shifted toward digital tools.
Cadence has been forced to invest aggressively to challenge Synopsys in this domain, developing competing digital implementation and signoff tools to win business at NVIDIA, Apple, and Google. This is a high-stakes gamble. If Cadence fails to achieve technological parity, it risks losing the entire customer relationship; design teams prefer unified tool flows and will consolidate with a single vendor to avoid integration risks. But if Cadence succeeds in digital, it gains share at the cost of compressing margins across the portfolio. Digital tools are more commoditized than analog tools, with higher R&D requirements and lower differentiation. The investment necessary to compete with Synopsys in AI chip design cannibalizes the high-margin analog business that historically funded the company’s profitability.
This dynamic creates a state of permanent competitive exhaustion. Cadence cannot afford not to compete in digital, but winning comes at the cost of profitability. The duopoly structure means there is no third player to absorb the competitive pressure; Cadence and Synopsys must match each other feature for feature, spending hundreds of millions annually on R&D to maintain a technological equilibrium that prevents customer defection but generates no pricing power.
When the Physics Debt Comes Due
Beneath these operational tensions lies a single fragile assumption: that Moore’s Law will continue to advance at its historical cadence for the next decade. Cadence’s financial model assumes that customers will redesign chips every two years, triggering re-licensing events with predictable regularity. If the physics of silicon or the economics of foundry investment interrupt this rhythm, the consequences would be immediate and severe.
The signs of strain are visible. The cost of designing a leading-edge chip has reached $500 million or more. Each new node requires exponentially more complex software to manage variability, thermal constraints, and quantum effects. At some point, perhaps at 2 nanometers, perhaps at 1.4, the economic returns of further shrinkage may no longer justify the cost, or the physical limits of gate oxide thickness may simply prevent further scaling. TSMC has already begun emphasizing chiplet architectures, where complex systems are built from smaller, proven die connected by advanced packaging rather than monolithic redesigns. If the industry shifts decisively toward chiplets, the frequency of full redesigns would decrease, and with it, the frequency of Cadence’s licensing opportunities.
The company is not blind to this risk. It has invested in system design tools, packaging solutions, and AI-driven optimization to capture value from the integration of multiple dies. But these are nascent markets compared to the mature, high-margin business of node-transition design. A prolonged pause in Moore’s Law would not merely slow growth; it would transform Cadence from a growth stock into a mature cash-flow business, valued on entirely different metrics.
The Concentration of Consequence
Compounding this fragility is an extreme concentration of revenue. While Cadence serves hundreds of customers, a disproportionate share of its revenue derives from the top ten semiconductor spenders: Apple, NVIDIA, Google, Amazon, Samsung, Intel, AMD, Broadcom, Qualcomm, and Microsoft. These companies are not merely customers; they are the primary drivers of process node advancement. If one were to shift strategy, if Apple decided to extend the lifecycle of its A-series chips to three years instead of two, or if NVIDIA acquired AMD and consolidated design teams, the impact on Cadence’s forecast would be material.
There is no hedge against this concentration. The switching costs that protect Cadence from competition also prevent customers from leaving, but they do not prevent customers from designing fewer chips or extending design cycles. In a severe semiconductor downturn, these mega-customers could reduce R&D budgets, delaying node transitions. Unlike a factory that can be idled and restarted, EDA subscriptions represent ongoing commitments, but they can be downsized. A customer cannot easily switch from Cadence to Synopsys, but they can negotiate reduced tool counts, delay emulation purchases, or extend design cycles to reduce annual spend.
The Piracy Shadow
One final fragility lurks in the accounting: unlicensed use. EDA software remains structurally vulnerable to piracy, particularly in regions with weak intellectual property enforcement. A cracked version of Cadence’s Virtuoso or Genus tools provides nearly identical functionality to the licensed version for a design team willing to operate in legal gray areas. While large, Western hyperscalers would never risk the compliance violations, smaller startups and certain international competitors may not share these constraints. Every unlicensed installation represents not merely lost revenue, but a potential future competitor trained on Cadence’s interface and methodology. Unlike enterprise software that requires cloud authentication or server infrastructure, many EDA tools can operate in air-gapped environments, making enforcement nearly impossible.
The Mechanics of Indispensability
Cadence is not a software company in the modern sense. It does not scale through network effects or viral adoption. It does not benefit from winner-take-all dynamics. Instead, it operates as a regulated utility within a duopoly, extracting predictable rents from a technological progression that predates the company and may outlast it. Its value is derived from the impossibility of substitution, witching costs measured not in months of migration, but in the risk of ten-million-dollar photomasks and two-year design cycles.
The business is both extraordinarily stable and fundamentally contingent. Stable because the combination of duopoly structure, infinite switching costs, and mission-critical utility makes customer churn virtually nonexistent. Contingent because the entire edifice rests on the continued viability of Moore’s Law and the continued willingness of five or six mega-customers to spend billions on leading-edge R&D.
Cadence captures value at the narrowest point in the semiconductor supply chain: the moment when abstract architecture becomes physical design. It is a tax collector, but the tax is voluntary in the sense that payment is the only alternative to obsolescence. The company will remain indispensable as long as silicon continues to shrink, and it will remain vulnerable the moment that shrinkage stops.
The cultural transformation that accompanied the 2008 turnaround is worth examining as an economic variable in its own right, distinct from the mechanical shift to subscriptions. When Lip-Bu Tan assumed interim leadership, he inherited not merely a broken revenue model but an organization that had lost its technical compass. Cadence had grown through acquisition in the 1990s and early 2000s, assembling a portfolio of tools that often competed with one another and bore little conceptual integration. Engineers spoke of “tool silos” where digital and analog teams used software with incompatible data formats, forcing manual translation of design databases that should have flowed seamlessly. The cost of this incoherence was not merely inefficiency; it was measured in failed tape-outs and customer defections to Synopsys, which had invested in unified database architectures.
Tan’s intervention was surgical. He canceled peripheral product lines that generated revenue but consumed engineering resources, accepting an immediate top-line hit to concentrate R&D on what he termed “the kernel”: he core algorithms for placement, routing, and verification that determine whether a chip meets timing constraints. This was not cost-cutting in the conventional sense; headcount actually stabilized. Rather, it was a reallocation of human capital away from maintenance and toward what economists would recognize as increasing returns to scale: the compounding value of cumulative refinement in complex optimization problems. A placement algorithm that is five percent faster does not merely save compute cycles; it allows chip architects to attempt more aggressive designs, which in turn reveals edge cases that improve the next iteration of the algorithm. Tan understood that in EDA, technical debt is literal debt, nterest payments made in the form of delayed revenue when customers cannot close timing.
The governance implications extended to customer relationships. Prior to 2008, Cadence had treated its largest accounts as transactional adversaries, negotiating each license as a zero-sum extraction of surplus. Tan instituted what the company internally called “co-development partnerships”, ulti-year agreements where Cadence engineers embedded directly with customer design teams at Apple, NVIDIA, and Qualcomm. This was economically irrational by traditional software metrics; the cost of sales rose dramatically as Cadence allocated precious engineering talent to customer premises rather than product development. But it solved a coordination problem. By placing Cadence employees inside customer workflows, the company gained visibility into the architectural roadmaps that would drive future tool requirements. When Apple decided to migrate from Intel processors to its own ARM-based silicon, Cadence had already adapted its power analysis tools for the specific voltage islands that would characterize the M1 chip. The embedded engineers were not merely support staff; they were intelligence assets, mapping the topology of future demand.
This cultural pivot, from vendor to partner, from transactional to structural, explains why Cadence’s net revenue retention consistently exceeds one hundred percent despite the duopoly. Customers do not merely renew; they expand their commitments because the software has been calibrated to their specific methodology. The switching costs, already high due to training and workflow embedding, become stratospheric when the tools themselves contain proprietary adaptations for a customer’s design style. A Qualcomm engineer attempting to migrate to Synopsys would discover not merely unfamiliar hotkeys, but the absence of optimizations specifically crafted for Qualcomm’s preferred clock-gating strategies. This is not lock-in through malice; it is lock-in through co-evolution, a mutual adaptation that makes separation biologically impossible without killing the host.
Yet this intimacy creates its own tension when the customer base expands beyond traditional semiconductor firms. When Ford Motor Company announced its initiative to design its own chips for electric vehicles, joining the ranks of hyperscalers and automotive OEMs entering silicon design, the economic profile of the relationship differed fundamentally from that with Qualcomm or Broadcom. Ford possessed no internal EDA expertise, no established design methodology, and no accumulated intellectual property regarding physical verification. The company required not merely software licenses but methodological consulting, training programs, and integration services that scaled with labor rather than with license value.
For Cadence, this represents a margin compression event disguised as growth. A traditional semiconductor customer might pay three million dollars annually for a suite of tools with minimal support overhead; Ford might pay five hundred thousand dollars for a limited tool suite but require two million dollars in consulting services to achieve basic productivity. The revenue is lower quality, ore contingent on labor inputs, less scalable, and vulnerable to cancellation if Ford’s automotive strategy shifts. Moreover, these new entrants design simpler chips, microcontrollers and power management ICs rather than massive SoCs, meaning they do not require the full spectrum of high-value verification and emulation tools that drive Cadence’s margin expansion. The democratization of chip design expands the addressable market, but it may simultaneously reduce the average revenue per customer and increase the cost to serve, creating a tension between volume and profitability that the company has not yet resolved.
The geographic dimension of this expansion introduces additional fragility. China represents the fastest-growing region for semiconductor R&D investment, with indigenous design houses proliferating under government subsidy programs. Cadence is legally obligated to serve this market, shareholder value demands participation in the largest growth vector, but the revenue quality is suspect. Intellectual property enforcement in certain jurisdictions remains theoretical; unlicensed installations of EDA tools are endemic, and the cost of audit and enforcement often exceeds the recoverable revenue. More critically, the geopolitical dynamics of semiconductor technology create regulatory tail risks. Export control regimes can shift abruptly, potentially prohibiting the sale of advanced EDA tools to specific Chinese entities overnight. Unlike a hardware shipment that can be redirected or warehoused, software sales are binary, either permitted or prohibited, with no salvage value for development costs already sunk.
The piracy issue extends beyond lost revenue to competitive dynamics. A startup in Shenzhen operating on unlicensed Cadence software gains competence in the company’s tool flow without contributing to R&D amortization. If that startup succeeds, it may eventually purchase legitimate licenses, but in the interim, it competes with legitimate customers who bear the full cost of the software tax. Worse, widespread unlicensed use creates a generation of engineers trained on Cadence’s interface and methodology, making it the default standard, ut this network effect does not translate to revenue if the standard is adopted through theft rather than commerce. The company faces the classical dilemma of the intellectual property vendor in emerging markets: enforcement alienates potential future customers, while toleration erodes the pricing power that funds innovation.
These pressures converge on the central strategic tension that Cadence must navigate over the next decade: the transition from monolithic SoC design to chiplet-based architectures. The industry is approaching a physical and economic limit where the cost of manufacturing a massive die on the most advanced node exceeds the value of the performance improvement. The solution, disaggregating processors into smaller “chiplets” connected by advanced packaging, threatens to break the two-year redesign cycle that underpins Cadence’s subscription model. If a company can mix and match proven chiplets, using a 5-nanometer compute die alongside a 7-nanometer I/O die and a mature-node memory controller, rather than redesigning a monolithic 3-nanometer chip, the frequency of full EDA tool utilization declines. The integration task shifts from transistor-level design to system-level packaging, requiring different software tools with different margin structures.
Cadence has invested in this transition, acquiring packaging and system-level design capabilities, but the economic implications are ambiguous. Packaging design requires less computational intensity than transistor-level place-and-route; the software is less mission-critical because the cost of error is lower (a failed interposer connection costs thousands to respin, not millions). If the industry shifts decisively toward chiplets, Cadence’s revenue per design could fall by half even as the number of designs increases, a trade-off that might satisfy growth metrics but destroy the margin expansion narrative that supports the company’s valuation multiple.
The bear case, then, is not a sudden collapse but a gradual compression of the revenue treadmill. Imagine a scenario where TSMC announces that the transition to 2-nanometer technology will be delayed to three years due to yield challenges, and simultaneously, the major hyperscalers, having built internal chip design capabilities over the past decade, achieve sufficient maturity to extend their chip lifecycles. Apple, having reached performance parity with its M-series chips for laptop applications, sees diminishing returns from annual silicon updates and moves to a thirty-six-month refresh cycle. NVIDIA, facing data center market saturation, slows the pace of GPU architectural transitions. The combination of longer node cadence and longer product lifecycles extends the average EDA contract renewal interval from two years to three.
The transmission mechanism to Cadence’s income statement would operate through several channels. First, the subscription model, while smoothing revenue, creates a ratchet effect; customers can downsize tool counts at renewal, but they rarely expand them mid-cycle. A lengthening design cycle means fewer renewal events per decade, reducing the opportunities to capture pricing increases. Second, the R&D burden remains fixed. Cadence must continue spending twenty percent of revenue on engineering to maintain parity with Synopsys regardless of customer refresh rates; if revenue growth stalls while R&D grows, operating margins compress. Third, the concentration risk becomes acute. If three of the top five customers simultaneously extend design cycles, Cadence cannot replace that revenue with new entrants because the new entrants (Ford, Amazon’s IoT division, automotive startups) operate on smaller scales and cannot absorb the tool volume of an Apple or NVIDIA.
In this scenario, Cadence does not become unprofitable; the duopoly ensures that existing customers remain captive, and the installed base generates substantial cash flow. But the company transitions from a growth stock valued on future expansion to a mature utility valued on current yield. The forty-billion-dollar market cap assumes continued Moore’s Law cadence; a deceleration would force a multiple re-rating that could halve the company’s value without impairing its ability to generate cash.
The duopoly with Synopsys, meanwhile, creates a peculiar stability that masks underlying competitive exhaustion. The two companies do not compete on price; they compete on capability coverage and customer intimacy. When Cadence wins a digital design slot at a major customer, it is not because it undercut Synopsys; it is because it offered emulation capabilities that Synopsys could not match, or because it embedded engineers more deeply in the customer’s flow. This is competition as mutual deterrence, where the goal is not to destroy the rival but to prevent the customer from consolidating entirely with them. The result is a comfortable stasis where both companies earn thirty percent operating margins while spending prodigiously on R&D that largely cancels out.
Yet this stasis depends on technological continuity. If artificial intelligence fundamentally changes the nature of chip design, if machine learning models can generate optimal floorplans in hours rather than months, the accumulated IP of both Cadence and Synopsys becomes less valuable. The current generation of AI-assisted design tools, marketed under names like Cerebrus, represents an incremental optimization; they improve existing algorithms but do not replace them. A disruptive shift, where the design problem becomes a data problem and the solution lies in training sets rather than heuristics, could theoretically lower the barriers to entry. Google’s internal chip design teams already experiment with reinforcement learning for placement; if such techniques generalize and become commoditized, the moat of accumulated EDA expertise erodes.
Cadence’s response to this threat has been to incorporate AI into its existing tools, arguing that the complexity of leading-edge design will always require human-AI collaboration rather than AI replacement. This may be correct; the physical constraints of electromigration and thermal management at 2 nanometers are not merely computational problems but physical problems requiring deep domain knowledge. But it represents a bet that the nature of design complexity remains constant. If chips become simpler, if the industry retreats to larger nodes for power efficiency, or if chiplets reduce the complexity of individual components, the value of sophisticated EDA tools diminishes proportionally.
The company thus finds itself defending a technological frontier that may be retreating. It must invest enough in digital design to prevent Synopsys from capturing the AI chip market, while maintaining analog dominance, while pivoting to packaging and system design, while serving new customers who lack expertise, all while extracting predictable revenue from a concentrated customer base that faces its own margin pressures. The subscription model provides stability but eliminates windfall pricing. The duopoly provides pricing power but demands continuous R&D parity. The Moore’s Law treadmill provides growth but assumes physics and economics will cooperate for another decade.
Cadence is not a bet on semiconductor demand broadly; it is a bet on the specific mechanics of node advancement and design complexity. It captures value at the moment of maximum uncertainty, when architecture becomes physics, and it captures that value reliably because the cost of error is catastrophic and the cost of switching is prohibitive. As long as companies must shrink transistors to compete, they will pay the tax. When shrinking stops, the tax code changes.